B=DISABLED, PC=ACTIVE_LOW, PB=HIGH, P=NONE, EW=DISABLED, PM=DISABLED, MW=8_BIT
Selects the memory configuration for static chip select 0.
| MW | Memory width. 0 (8_BIT): 8 bit (POR reset value). 1 (16_BIT): 16 bit. 2 (32_BIT): 32 bit. 3 (RESERVED): Reserved. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| PM | Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally. 0 (DISABLED): Disabled. (POR reset value.) 1 (ENABLED): Enabled. Async page mode enabled (page length four). |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| PC | Chip select polarity. The value of the chip select polarity on power-on reset is 0. 0 (ACTIVE_LOW): Active LOW chip select. 1 (ACTIVE_HIGH): Active HIGH chip select. |
| PB | Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal. 0 (HIGH): High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value). 1 (LOW): Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW. |
| EW | Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1] 0 (DISABLED): Disabled. Extended wait disabled (POR reset value). 1 (ENABLED): Enabled. Extended wait enabled. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| B | Buffer enable [2]. 0 (DISABLED): Disabled. Buffer disabled (POR reset value). 1 (ENABLED): Enabled. Buffer enabled. |
| P | Write protect. 0 (NONE): None. Writes not protected (POR reset value). 1 (PROTECT): Protect. Write protected. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |